• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to an input buffer circuit of a semiconductor device for improving the characteristics of a high level input signal VIH (VOLTAGE INPUT HIGH) and a low level input signal VIL (VOLTAGE INPUT LOW). In the input buffer of a semiconductor device for changing VICC / VIL simultaneously to VCC / 2, input signals output from the first and second input buffer means and then output high signals to improve the characteristics of the VIH. VIH / VIL determining means for inputting signals output from the third and fourth input buffer means and then outputting a low signal to improve the characteristics of the VIL; And differential amplifying means for differentially amplifying the output high signal of the VIH / VIL determining means applied to the high signal applying stage by the output low signal of the VIH / VIL determining means applied to the low signal applying stage and outputting the output high signal to the output stage. .
    公开号:KR19980058431A
    申请号:KR1019960077755
    申请日:1996-12-30
    公开日:1998-10-07
    发明作者:박근우；허용진；안상민；이종문
    申请人:김영환；현대전자산업 주식회사；
    IPC主号:
    专利说明:

    Input buffer circuit of semiconductor device
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input buffer circuit of a semiconductor device, and more particularly to a semiconductor device for improving characteristics of a high level input signal VIH (VOLTAGE INPUT HIGH) and a low level input signal VIL (VOLTAGE INPUT LOW). Is related to the wear buffer circuit.
    In general, an input buffer is for inputting an input signal input through a pad to a DRAM device. The input buffer determines a high / low state of an external signal having a TTL (Transistor Transistor Logic) potential input at approximately 2.0 V / 0.8 V. It switches to VCC / 0V, a CMOS level that can be used inside DRAM devices.
    Conventional input buffers have buffer logic thresholds in VCC / 2 in the form of NOR GATE and NAND GATE to satisfy the characteristics of VIH / VIL with one input buffer. .
    Referring to FIG. 1, in the conventional input buffer, (a) is an output characteristic of VOUT (OUTPUT VOLTAGE) to VIN (INPUT VOLTAGE) of the input buffer, (b) is the size of VIL, and (c) Size.
    However, such conventional input buffers satisfy logic VIH / VIL simultaneously with one input buffer by placing a logic threshold on VCC / 2, and therefore, either VH or VIL due to VCC / VSS noise. When the characteristics deteriorate and the voltage near the logic threshold is applied to the input, the input buffer has a problem of slow operation speed and malfunction.
    Accordingly, the present invention is to solve such a problem, the input buffer of the semiconductor device that can improve the characteristics of the VIH / VIL by combining the output of the two input buffers with the logic threshold voltage changed to the NOR gate and the NAND gate The purpose is to provide a circuit.
    1 is a characteristic diagram of an input voltage of a conventional input buffer.
    2A and 2B are circuit diagrams of an input buffer according to an embodiment of the present invention.
    3 is a circuit diagram of VIH / VIL determining means in accordance with an embodiment of the present invention.
    4 is a circuit diagram of differential amplification means for differentially amplifying the output of FIG.
    5 is a characteristic diagram of an output and an input voltage according to an embodiment of the present invention.
    Explanation of symbols on the main parts of the drawings
    1: first input buffer means, 2: second input buffer means, 1 ': third input buffer means, 2': fourth input buffer means, 3: noah gate, 4: NAND gate, 5: VIH / VIL determination Means, 5-1: VIH determination means, 5-2: VIL determination means, 6,7,9,10: MOS transistor, 11: differential amplification means
    The input buffer circuit of the semiconductor device of the present invention for achieving the above object is a first and second input buffer in the input buffer of the semiconductor device to improve the VIH / VIL at the same time by changing the logic threshold voltage to VCC / 2 VIH for inputting a signal output from the means and then outputting a high signal to improve the characteristics of the VIH, and a VIH for inputting a signal output from the third and fourth input buffer means and then outputting a low signal to improve the characteristics of the VIL. / VIL determining means; And differential amplifying means for differentially amplifying the output high signal of the VIH / VIL determining means applied to the high signal applying stage by the output low signal of the VIH / VIL determining means applied to the low signal applying stage and outputting the output high signal to the output stage. It is characterized by.
    EXAMPLE
    Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 2, 3, 4, and 5.
    Referring to FIG. 2A, the first input buffer means 1 of the present invention is connected between the power supply voltage VCC and the ground voltage VSS. The low input signal is one input and VIN (INPUT VOLTAGE) is used. A NOR gate NOR for outputting to the output stage as a type force is provided.
    The first input buffer means 1 changes the buffer logic threshold voltage approximately -0.5V.
    Referring to FIG. 2B, the second input buffer means of the present invention is connected between a power supply voltage and a ground voltage, and outputs the NAND gate to the output terminal with the HIGH signal as one input and the VIN as the type force. It is provided.
    The second input buffer means 2 changes the buffer logic threshold voltage by approximately + 0.5.V.
    3 illustrates a circuit diagram of an input buffer according to an embodiment of the present invention.
    Referring to FIG. 3, the input buffer according to the present invention largely differentially amplifies the VIH / VIL determining means 5 and the high outputs of the VIH / VIL determining means 5 and outputs them as final buffer outputs. It is provided.
    The VIH / VIL deciding means 5 is constituted by VIH deciding means and VIL deciding means which take a VIN signal as an input signal.
    The VIH determining means 5-1 includes a first input buffer means 1 having VIN as an input signal, an input buffer means 2 having VIN as an input signal, and a first input buffer means 1 with one input. And a NOR gate (3) for inputting the output of the input signal and inputting the output of the second input buffer means (2) with a type force to output a high signal.
    Since the output of the VIH determining means 5-1 is determined by the VIH of the first input buffer means 1, it is possible to determine the HIGH LEVEL even for a lower VIN, which is an advantage of the first input buffer means 1. Can only take
    On the other hand, the VIL determining means 5-2 of the present invention includes a first input buffer means 1 having VIN as an input signal, a second input buffer means 2 having VIN as an input signal, and a first input. A NAND gate 4 is provided which inputs the output of the third input buffer means 1 ', inputs the output of the fourth input buffer means 2' by the type force, logically multiplies, and inverts it to output a low signal.
    The third input buffer means 1 'and the fourth input buffer means 2' have the same configuration and operation as the first and second input buffer means 1, 2.
    Since the output of the VIL determining means 5-2 is determined by the VIL of the fourth input buffer means 2 ', the low level LOW LEVEL can be determined even for a higher VIN. Can only take advantage of.
    4 shows a circuit diagram of differential amplifying means 11 of an input buffer according to an embodiment of the invention.
    4, the differential amplification means 11 of the present invention is for differential amplification, in which the output high signal of the VIH determining means 5-1 and the output low signal of the VIL determining means 5-2 are applied to the gate, respectively. The first and second N-MOS transistors 6 and 7, the third and fourth N-MOS transistors 8 and 9 for current mirrors connected to the drains of the first and second N-MOS transistors 6 and 7, and a gate A fifth MOS transistor 10 is applied to which the reference voltage VREF is applied and is connected to the sources of the first and second NMOS transistors 6 and 7 for differential amplification and serves as a current source.
    The differential amplifying means 11 is a part of the VIL determining means 5-2 that applies the output high signal of the VIH determining means 5-1 applied to the high signal applying end HIGH to the low signal applying end LOW. Differential amplification according to the output low signal and output through the output stage.
    Therefore, the differential amplification means 11 has a VIH equal to 1.7 equal to the VIH of the first input buffer means 1, and VIL equals 1.2 V equal to the VIL of the second input buffer means 2, thereby providing a conventional input buffer. By reducing the area of malfunctions generated, the characteristics of the VIH / VIL can be improved simultaneously.
    Table 1 below shows the VIL / VIH of the first, second and third input buffers 1, 2 and 11 of the present invention.
    TABLE 1
    Table 2 below shows the results of simulations on the input levels of the first, second and third input buffers 1, 2, 11 of the present invention.
    TABLE 2
    In Table 2, L is LOW, m is difficult to determine HIGH / LOW, indicating malfunction, and H is HIGH LEVEL.
    Referring to Fig. 5, the output characteristics and VIN / VIH of VOUT with respect to VIN of the first and second input buffer means 1, 2 of the present invention will be described.
    Referring to FIG. 5, (a) is an output characteristic of a conventional input buffer, (b) is an output characteristic of the first input buffer means 1, and (c) is an output of the second input buffer means 2. (D) is the conventional VIL, (f) is the VIL of the input buffer of the present invention, (g) is the VIH of the conventional input buffer, and (g) is the VIH of the input buffer of the present invention.
    As described above, the input buffer circuit of the semiconductor device of the present invention combines the outputs of two trapping buffers having changed logic threshold voltages with a NOR gate and a NAND gate to improve the characteristics of VIH / VIL, thereby improving operation speed. Speed up and provide excellent effect to prevent malfunction.
    权利要求:
    Claims (8)
    [1" claim-type="Currently amended] In the input buffer of a semiconductor device for changing VIH / VIL at the same time by changing the logic threshold voltage to VCC / 2, the characteristics of the VIH by inputting a signal output from the first and second input buffer means and then outputting a high signal VIH / VIL determining means for inputting a signal output from the third and fourth input buffer means and then outputting a low signal to improve the characteristics of the VIL; And differential amplifying means for differentially amplifying the output high signal of the VIH / VIL determining means applied to the high signal applying stage by the output low signal of the VIH / VIL determining means applied to the low signal applying stage and outputting the output high signal to the output stage. An input buffer circuit of a semiconductor device, characterized in that.
    [2" claim-type="Currently amended] 2. The input buffer circuit according to claim 1, wherein the VIH / VIL determining means comprises VIH determining means for improving the characteristics of the VIH and VIL determining means for improving the characteristics of the VIL.
    [3" claim-type="Currently amended] 3. The input buffer circuit as claimed in claim 2, wherein the VIH determining means includes a NOR gate for outputting a high signal by logically inputting the signals in order to improve the characteristics of the VIH.
    [4" claim-type="Currently amended] 3. The input buffer circuit of claim 2, wherein the VIL determining means comprises a NAND gate for outputting a low signal by logic NAND to improve the characteristics of the VIL.
    [5" claim-type="Currently amended] The semiconductor device according to claim 1, wherein the first input buffer means is connected between a power supply voltage and a ground voltage, and has a NOR gate for outputting a low signal as one input and a VIN as a type force. Input buffer circuit.
    [6" claim-type="Currently amended] 2. The semiconductor device as claimed in claim 1, wherein the second input buffer means has a NAND gate connected between a power supply voltage and a ground voltage and outputs a high signal as one input and a VIN as a type force. Input buffer circuit.
    [7" claim-type="Currently amended] The semiconductor device according to claim 1, wherein the third input buffer means has a NOR gate connected between a power supply voltage and a ground voltage and outputting a low signal as one input and a VIN as a type force. Input buffer circuit.
    [8" claim-type="Currently amended] The semiconductor device according to claim 1, wherein the fourth input buffer means has a NAND gate connected between a power supply voltage and a ground voltage and outputs a high signal as one input and a VIN as a type force. Input buffer circuit.
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    同族专利:
    公开号 | 公开日
    KR100247638B1|2000-03-15|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1996-12-30|Application filed by 김영환, 현대전자산업 주식회사
    1996-12-30|Priority to KR1019960077755A
    1998-10-07|Publication of KR19980058431A
    2000-03-15|Application granted
    2000-03-15|Publication of KR100247638B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019960077755A|KR100247638B1|1996-12-30|1996-12-30|Input buffer circuit of semiconductor device|
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